| PART |
Description |
Maker |
| KS74AHCT112 |
Dual J-K Negative-Edge-Triggered Flip-Flops
|
Samsung
|
| SN74LS113D SN74LS113N SN54LS113J SN54LS113A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
|
| SN74LS107D SN74LS107N SN54LS107J SN54LS107A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
Motorola Inc
MOTOROLA[Motorola Inc]
|
| SN74LS114D SN54LS114J SN74LS114N SN54LS114A SN5474 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
MOTOROLA[Motorola Inc]
|
| SN54LS113A SN74LS113A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP JK负边沿触发器
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| 74F112 I74F112D I74F112N N74F112D N74F112N 74F112_ |
From old datasheet system
Dual J-K negative edge-triggered flip-flop
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| 74F114PC |
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
|
Fairchild Semiconductor
|
| MC74HC107DR2 |
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
MOTOROLA INC
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
| CD74HCT73E |
<font color=red>[Old version datasheet]</font> Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
TI store
|
